Assignment – A

Q1 a): Prove the Demorgan’s laws using Boolean algebra.

Q1 b): Find the minimal sum of product expression for the following Switching

function. F (x1, x2, x3, x4, x5) = Sm (1, 2, 3, 6, 8, 9, 14, 17, 24, 25, 26, 27, 30,31) + Sd(4,5)

Q2 a): Explain the working of master-slave JK flip flop. State its merit. What is Race problem in flip- flops?

Q2 b): Design a negative edge triggered T flip flop. The circuit has two inputs, T(toggle) and C(clock) and output Q and Q’. The output state is

complemented if T=1 and the clock C changes from 1 to 0. Otherwise under any other input condition, the output Q remains unchanged.

Q3 a) Differentiate between:

i) Combinational and Sequential Logic Circuits,

ii) Synchronous and Asynchronous Counters

Q4 Do as directed

a) Conversion of 100.55 base 10 into binary, octal codes.

b) Conversion of 1111010011011110 base 2 to decimal, hexadecimal.

Q5 a) Draw the circuit of a 3 to 8 decoder and explain its operation. How this can be used as a DEMUX.

Q5 b): Design and explain Priority encoder.

Assignment -B

Q1 A Gray code is a sequence of codes which differ in one bit position at each step. For example 00, 01, 11, 10, 00 … is a two-bit Gray code. Design a counter made from JK flip-flops to produce a three-bit Gray code.

Q2 Mention the various A/D convertors. And Draw and discuss the circuit of a dual scope A/D convertor. Also discuss the comparison of advantages and disadvantages of each of A/D convertor.

Q3 Draw the circuit of a 4-bit shift registers and explains its operation. Also explain Various different types of shift register with circuit diagram.

Case Study

An m: 1 multiplexer has m data inputs; log2m control signals and produces a data output which is equal to the input selected by the control signals. Each different combination of control signals selects a different input. Present an implementation, either as a circuit diagram or as equations, of an 8: 1 multiplexer. Show how 8: 1 multiplexers can be cascaded to build a 64: 1 multiplexer.

ASSIGNMENT – C

Q1 8421 code is

a) Self-complementing code

b) Weighted code

c) Non-weighted code

d) Alphanumeric code

Q2 ASCII code is a

a) 5-bit code

b) 7-bit code

c) 8-bit code

d) 10-bit code

Q3 In synchronous counters the clock input of each of the bi-stables are connected together so that each changes state at the same time.

a) True

b) False

Q4 Decimal that converts from decimal to binary numbered is called______

a) Encoder

b) Decoder

c) Converter

d) CPU

Q5 The binary number 101100.110 in octal number will be

a) 152.6

b) 154.6

c) 145.2

d) 174.5

Q6 64K is ______

a) 6400

b) 64000

c) 65536

d) 64536

Q7 Binary 1000 will be the result of which of the following

a) Binary 1000-100

b) Binary 1011-1111

c) Binary 1111-111

d) Binary 11111-1111

Q8 Decimal 14 in binary system can be written as

a) 1111

b) 1110

c) 0111

d) 1100

Q9 In digital electronics, which of the following voltage levels does not denote logic ‘0’?

a. O volt

b. 0.4 volt

c. <0.8volt

d. none of the above

Q10 Aside from the binary system, what other number system is commonly used in digital systems?

a. decimal

b. hexadecimal

c. scale-of-2

d. none of the above

Q11 1n Boolean algebra the OR function is represented by the ‘+’ sign.

a) True

b) False

Q12 A signal having discrete values is known as

a) a digital signal

b) an analog signal

c) a natural signal

d) none of the above

Q13 How many nibbles count in the number 1111 1110?

a) 4

b) 8

c) 2

d) 16

Q14 If 2 in binary system 010 then 6 will be

a) Oil

b) 0111

c) 1110

d) None of the above

Q15 What is binary equivalent of FC6 is ________

a) 11111100 0110

b) 011011001010

c) None of the above

d) Both of the above

Q16 The 2’s complement of 100001011 is _________

a) 011110101

b) 001110100

c)

d) 001111100

e) 000110100

Q17 Which of the following are universal gate:

a) AND

b) NAND

c) NOR

d) OR

Q18 Which logic gate has the following tmth table?

Input | Input | Output |

A | B | c |

0 | 0 | 1 |

0 | 1 | 0 |

1 | 0 | 0 |

1 | 1 | 0 |

a) An exclusive NOR gate.

b) A two-input AND gate.

c) A two-input OR gate.

d) An exclusive OR gate

Q19 In which gate output is complements of its input:

a) AND

b) NOT

c) NOR

d) None of the above

Q20 In the Karnaugh map shown below, which of the loops shown represents a legal grouping?

a) A

b) B

c) C

d) D

Q21 How many gate inputs are required to realize the following expression?

F=(B+C+D)(B+C+E)(A+B+C+E)(F+G)

a) 14

b) 15

c) 16

d) All the above

Q22 How many cells present in a 4-variable format?

a) 16

b) 8

c) 32

d) None of the above

Q23 Is in positive logic circuits it is normal to use +5V for true and OV for false?

a) True

b) False

Q24 A logic circuit that accepts one data input and distributes it over several outputs is known as______

a) Decoder

b) DMUX

c) Priority Encoder

d) All of the above

Q25 The below circuit diagram is:

a) 2-to-4 bit Binary decoder

b) 4-to-2 bit Binary decoder

c) 2-to-4 bit Priority decoder

d) None of the above

Q26 A full adder can be made by adding____________ .

a) Two half adder

b) Two half subtractor

c) Both a and b

Q27 Master-Slave J-K flip-flop doesn’t solves the race around problem occurs in JK-flip-flop

a) True

b) False

Q28 In a ___________, the output of the last flip-flop is connected back to the input of the first flip-flop.

a) Johnson counter

b) Ring counter

c) D-type flip-flop

d) None of the above

Q29 How many flip-flops are needed for an 8-bit counter?

a) Two

b) Three

c) Four

d) Eight

Q30 Which of the following can be used in Keyboard encoder?

a) Shift registers

b) Flip-Flop

c) Registers

d) All of the above

Q31 DAC converts___________

a) Analog to Digital

b) Digital to Analog

c) Both a and b

Q32 (247.36)_{8} = (?)_{16}

a) A6.78

b) A7.78_

c) 78.A7

d) 78.A6

Q33 (3F)_{16}-(5C)_{16}= (_________)_{16}

a) Dl

b) 1D_

c) D2

d) DE

Q34 An array of flip-flop is also known as__________.

a) Counter

b) D Flip-Flop

c) Register

d) All of the above

Q35 Which of the following are based on digital systems?

a) Electronic calculator

b) Voting Machine

c) Traffic signal

d) None of the above

Q36 An OR gate is ENABLED by connecting one of its inputs to logic level______.

a) 0

b) 1

c) 0 or 1

d) None of the above

Q37 How many data inputs contains by a 64 output lines decoder?

a) 64

b) 6

c) 2

d) All of the above

Q38 A flip-flop with active low preset input will have Q’= ______when preset is counted to low.

a) 1

b) 0

c) 1 and 0

d) None of the above.

Q39 How many maximum possible number of states in a clocked sequential circuit having 6 Flip-flops?

a) 32

b) 64

c) 16

d) None of the above

Q40 A dynamic RAM is fabricated using___________technology.

a) CMOS

b) MOS

c) CHIP

d) none

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